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MK2059-01
VCXO-Based Frame Clock Frequency Translator
Description
The MK2059-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that produces common telecommunications reference frequencies. The output clock is phase locked to an 8kHz (frame rate) input reference clock. The MK2059-01 also provides jitter attenuation. Included in the selection of output frequencies are these common system clocks: 1.544 MHz (T1) 19.44 MHz (OC-3) 2.048 (E1) 16.384 MHz (8x E1)
Features
* Generates T1, E1, OC-3 and other common telecom * * * * * * * * * *
clock frequencies from an 8kHz frame clock Configurable jitter attenuation characterisitics, excellent for use as a Stratum source de-jitter circuit 2:1 Input MUX for input reference clocks VCXO-based clock generation offers very low jitter and phase noise generation Output clock is phase and frequency locked to the selected input reference clock Fixed input to output phase relationship +115ppm minimum crystal frequency pullability range, using recommended crystal Industrial temperature range Low power CMOS technology 20 pin SOIC package Single 3.3V power supply
This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. Through selection of external loop filter components, the PLL loop bandwidth and damping factor can be tailored to meet input clock jitter attenuation requirements. A loop bandwidth down to the Hz range is possible.
Block Diagram
P ullable x tal
VD D
IS E T
X1
X2
VDD
3
8kH z R ef In p ut 8kH z R ef In p ut
IC L K 2 IC L K 1
1 0
P h ase D etecto r C harg e P um p
V C XO
O u tpu t D ivid er
CLK
ISE L
F eedb ack D ivid er S EL 2:0
3
CHGP
VIN
GND
4
MDS 2059-01 B
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Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Pin Assignment
X1 VD D VD D VD D V IN GN D GN D GN D CHG P ISE T 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 X2 GND IS E L IC L K 1 IC L K 2 S EL 0 CLK NC S EL 1 S EL 2
Output Clock Selection Table
Input 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz SEL2 0 0 0 0 M M M M 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 Output Clock (MHz) 1.544 2.048 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576 Crystal Used (MHz) 24.704 24.576 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576
20 pin 300 mil SOIC
Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
X1 VDD VDD VDD VIN GND GND GND CHGP ISET SEL2 SEL1 NC CLK SEL0 ICLK2 ICLK1 ISEL GND X2
Pin Type
Power Power Power Input Power Power Power Output Input Input Input Output Input Input Input Input Power -
Pin Description
Crystal Input. Connect this pin to the specified crystal. Power Supply. Connect to +3.3V. Power Supply. Connect to +3.3V. Power Supply. Connect to +3.3V. VCXO Control Voltage Input. Connect this pin to CHGP pin and the external loop filter as shown in this data sheet. Connect to ground Connect to ground Connect to ground Charge Pump Output. Connect this pin to the external loop filter and to pin VIN. Charge pump current setting node, connection for setting resistor. Output Frequency Selection Pin 2. Determines output frequency as per table above. Internally biased to VDD/2. Output Frequency Selection Pin 1. Determines output frequency as per table above. Internal pull-up. No Internal Connection. Clock Output Output Frequency Selection Pin 0. Determines output frequency as per table above. Internal pull-up. Input Clock Connection 2. Connect an input reference clock to this pin. If unused, connect to ground. Input Clock Connection 1. Connect an input reference clock to this pin. If unused, connect to ground. Input Selection. Used to select which reference input clock is active. Low input level selects ICLK1, high input level selects ICLK2. Internal pull-up. Connect to ground. Crystal Output. Connect this pin to the specified crystal.
MDS 2059-01 B
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Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Functional Description
The MK2059-01 is a clock generator IC that generates an output clock directly from an internal VCXO circuit which works in conjunction with an external quartz crystal. The VCXO is controlled by an internal PLL (Phase Locked Loop) circuit, enabling the device to perform clock regeneration from an input reference clock. The MK2059-01 is configured to provide a MHz communications reference clock output from an 8kHz input clock. There are 12 selectable output frequencies. Please refer to the Output Clock Selection Table on Page 2. Most typical PLL clock devices use an internal VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO with an external crystal, the MK2059-01 is able to generate a low jitter, low phase-noise output clock within a low bandwidth PLL. This serves to provide input clock jitter attenuation and enables stable operation with a low frequency reference clock. The VCXO circuit requires an external pullable crystal for operation. External loop filter components enable a PLL configuration with low loop bandwidth.
Quartz Crystal
It is important that the correct type of quartz crystal is used with the MK2059-01. Failure to do so may result in reduced frequency pullability range, inability of the loop to lock, or excessive output phase jitter. The MK2059-01 operates by phase-locking the VCXO circuit to the input signal of the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the PCB Layout Recommendations section must be followed. The frequency of oscillation of a quartz crystal is determined by its cut and by the external load capacitance. The MK2059-01 incorporates variable load capacitors on-chip which "pull", or change, the frequency of the crystal. The crystals specified for use with the MK2059-01 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. To achieve this, the layout should use short traces between the MK2059-01 and the crystal. A complete description of the recommended crystal parameters is shown below.
Application Information
Output Frequency Configuration
The MK2059-01 is configured to generate a set of output frequencies from an 8kHz input clock. Please refer to the Output Clock Selection Table on Page 2. Input bits SEL2:0 are set according to this table, as is the external crystal frequency. Please refer to the Quartz Crystal section on this page regarding external crystal requirements.
Recommended Crystal Parameters: Operating Temperature Range Commercial Applications Industrial Applications Initial Accuracy at 25C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0 C0/C1 Ratio Equivalent Series Resistance 0 to 70C -40 to 85C 20 ppm 30 ppm 20 ppm Note 1 7 pF Max 250 Max 35 Max
Input Mux
The Input Mux serves to select between two alternate input reference clocks. Upon reselection of the input clock, clock glitches on the output clock will not be generated due to the "fly-wheel" effect of the VCXO (the quartz crystal is a high-Q tuned circuit). When the input clocks are not phase aligned, the phase of the output clock will change to reflect the phase of newly selected input at a controlled phase slope (rate of phase change) as influenced by the PLL loop characteristics.
Note 1: For crystal frequencies between 13.5MHz and 27MHz the nominal crystal load capacitance specification should be 14pF. Contact ICS MicroClock applications at (408) 297-1201 regarding the use of a crystal below 13.5MHz. To obtain a list of qualified crystal devices that meet these requirements, please contact ICS MicroClock applications department.
MDS 2059-01 B
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Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating stability. The MK2059-01 uses external loop filter components for the following reasons: 1) Larger loop filter capacitor values can be used, allowing a lower loop bandwidth. This enables the use of lower input clock reference frequencies and also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking is desired. 2) The loop filter values can be user selected to optimize loop response characteristics for a given application. Referencing the External Component Schematic on this page, the external loop filter is made up of components RZ, C1 and C2. RSET establishes PLL charge pump current and therefore influences loop filter characteristics.
External Component Schematic
CL
Do n't S tuff (R efer to O ptional C ry stal T uning section) X1 VDD VDD VDD VIN
CL
Xtal
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
X2 G ND IS EL IC LK 1 IC LK 2 S EL0 C LK NC S EL1 S EL2
C2
RZ C1
G ND G ND G ND C HG P IS ET
R S ET
Recommended Loop Filter Values Vs. Output Frequency Range Selection
Crystal
SEL2 SEL1 SEL0 Multiplier
RSET 120 k 120 k 120 k 120 k 120 k 120 k 120 k 120 k 120 k 120 k 120 k 120 k
RZ 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M 1.0 M
C1 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F
C2 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF
Loop Bandwidth
(-3dB point)
Damping Factor 1.4 1.4 1.7 1.7 1.6 1.6 1.4 1.4 1.6 1.6 1.4 1.4
0 0 0 0 M M M M 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
(N) 3088 3072 2048 2208 2316 2500 3125 3240 2430 2560 3088 3072
18 Hz 19 Hz 27 Hz 26 Hz 24 Hz 22 Hz 18 Hz 17 Hz 23 Hz 22 Hz 18 Hz 19 Hz
Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating
MDS 2059-01 B
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Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
A "normalized" PLL loop bandwidth may be calculated as follows: R Z x I CP x 575 NBW = --------------------------------------N The "normalized" bandwidth equation above does not take into account the effects of damping factor or the second pole. However, it does provide a useful approximation of filter performance. The loop damping factor is calculated as follows: 625 x I CP x C 1 Damping Factor = R Z x ---------------------------------------N Where: RZ = Value of resistor in loop filter (Ohms) ICP = Charge pump current (amps) (refer to Charge Pump Current Table, below) N = Crystal multiplier shown in the above table C1 = Value of capacitor C1 in loop filter (Farads) As a general rule, the following relationship should be maintained between components C1 and C2 in the loop filter: C2
1 = -----
1) The loop capacitors should be a low-leakage type to avoid leakage-induced phase noise. For this reason, DO NOT use any type of polarized or electrolytic capacitors. 2) Microphonics (mechanical board vibration) can also induce output phase noise, especially when the loop bandwidth is less than 1kHz. For this reason, ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R. These and some other ceramics have piezoelectric properties that convert mechanical vibration into voltage noise that interferes with VCXO operation. For larger loop capacitor values such as 0.1 F or 1 F, PPS film types made by Panasonic, or metal poly types made by Murata or Cornell Dubilier are recommended. For questions or changes regarding loop filter characteristics, please contact your sales area FAE, or ICS MicroClock Applications.
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. (The optional series termination resistor is not shown in the External Component Schematic.)
C
20
Decoupling Capacitors
As with any high performance mixed-signal IC, the MK2059-01 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK2059-01 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation.
Charge Pump Current Table
RSET 1.4 M 680 k 540 k 120 k Charge Pump Current (ICP) 10 A 20 A 25 A 100 A
Special considerations must be made in choosing loop components C1 and C2:
MDS 2059-01 B
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MK2059-01 VCXO-Based Frame Clock Frequency Translator
Recommended Power Supply Connection for Optimal Device Performance
V D D P in C onnection to 3.3V P ow er P lane Ferrite B ead V D D P in
as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. C2 should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 4) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output. 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK2059-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The ICS Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section.
B ulk D ecoupling C apacitor (such as 1 F Tantalum )
V D D P in
0.01 F D ecoupling C apacitors
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no via's) been the crystal and device. In most cases the load capacitors will not be required. They should not be stuffed on the prototype evaluation board as the indiscriminate use of these trim capacitors will typically cause more crystal centering error than their absence. If the need for the load capacitors is later determined, the values will fall within the 1-4 pf range. The need for, and value of, these trim capacitors can only be determined at prototype evaluation. Please refer to the Optimization of Crystal Load Capacitors section for more information.
Optimization of Crystal Load Capacitors
The concept behind the optional crystal load capacitors was introduced previously in this data sheet (see Crystal Load Capacitor section on Page 5). To determine the need for and value of these capacitors, you will need a PCB of your final layout, a frequency counter capable of less than 10 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors: 1. Connect VDD to 3.3V. Connect pin 5 to the second power supply. Adjust the voltage on pin 5 to 0V. Measure and record the frequency of the CLK output.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via's should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible,
MDS 2059-01 B
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MK2059-01 VCXO-Based Frame Clock Frequency Translator
2. Adjust the voltage on pin 5 to 3.3V. Measure and record the frequency of the same output. To calculate the centering error:
6 ( f 3.0V - f t arg et ) + ( f 0V - f t arg et ) Error = 10 x ------------------------------------------------------------------------------ - error xtal f t arg et
much stray capacitance and will need to be redone with a new layout to reduce stray capacitance. Alternately, the crystal may be re-specified for a higher lower load capacitance. Contact ICS MicroClock for details. If the centering error is more than 15 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: External Capacitor = 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (less than 15ppm).
Where: ftarget = nominal crystal frequency errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than 15 ppm, adjustment is not needed for most applications. If the centering error is more than 15 ppm negative, the PCB has too
Recommended PCB Layout
F or m in im u m ou tp ut clock jitte r, rem ove g ro un d an d p ow er pla ne w ithin this en tire a re a. A lso rou te a ll othe r traces aw a y from th is a re a.
G
F or m in im u m ou tp ut clock jitte r, d evice V D D con ne ctio ns sho uld b e m a de to co m m on bulk d eco up ling d evice (see te xt).
G G G
G
1 2 3 4 5 6 7 8 9 10
G
G G G
20 19 18 17 16 15 14 13 12 11
NC
L eg en d:
G G
= G ro un d C o nn ectio n
MDS 2059-01 B
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Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2059-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V -40 to +85C -65 to +150C 175C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
-40 +3.15
Typ.
- +3.3
Max.
+85 +3.45
Units
C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85C
Parameter
Operating Voltage Supply Current Input High Voltage, SEL2 Input Low Voltage, SEL2 Input High Voltage, ISEL, SEL1:0 Input Low Voltage, ISEL, SEL1:0 Input High Voltage, ICLK1, 2 Input Low Voltage, ICLK1, 2 Input High Current Input Low Current Input Capacitance, except X1
Symbol
VDD IDD VIH VIL VIH VIL VIH VIL IIH IIL CIN
Conditions
Clock outputs unloaded, VDD = 3.3V - - - - - - VIH = VDD VIL = 0 -
Min.
3.15
Typ.
3.3 10
Max.
3.45 15 - 0.5 - 0.8 -
VDD/2-1
Units
V mA V V V V V V A A pF
VDD-0.5 - 2 -
VDD/2+1
- - - - - - - - 7
- -10 -10 -
+10 +10 -
MDS 2059-01 B
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MK2059-01 VCXO-Based Frame Clock Frequency Translator
Parameter
Output High Voltage (CMOS Level) Output High Voltage Output Low Voltage Short Circuit Current VIN, VCXO Control Voltage Nominal Output Impedance
Symbol
VOH VOH VOL IOS VXC ZOUT
Conditions
IOH = -4 mA IOH = -8 mA IOL = 8 mA
Min.
VDD-0.4 2.4 - 0
Typ.
Max.
Units
V V
- 50
0.4 VDD
V mA V
20
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C
Parameter
VCXO Crystal Pull Range VCXO Crystal Nominal Frequency Input Jitter Tolerance Input pulse width (1) Output Frequency Error Output Duty Cycle (% high time) Output Rise Time Output Fall Time Skew, Input to Output Clock Cycle Jitter (short term jitter) Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) Timing Jitter, Filtered 65kHz-1.3MHz (OC-3)
Symbol
fXP fX tji tpi FOUT tOD tOR tOF tIO tja tjf
Conditions
Using Recommended Crystal
Min.
-115 13.5
Typ.
Max. Units
+115 27 0.4 ppm MHz UI ns
In reference to input clock period 10 ICLK = 0 ppm error Measured at VDD/2, CL=15pF 0.8 to 2.0V, CL=15pF 2.0 to 0.8V, CL=15pF Rising edges, CL=15pF Referenced to Mitel/Zarlink MT9045, Note 2 Referenced to Mitel/Zarlink MT9045, Note 2 -5 150 227 0 40 0 -
0 60 1.5 1.5 +5
ppm % ns ns ns ps p-p ps p-p
tjf
170
ps p-p
Note 1: Minimum high or low time of input clock. Note 2: Input reference is the 8 kHz output from a Mitel/Zarlink MT9045 device in freerun mode (SEL2:0 = 100, 19.44 MHz external crystal).
MDS 2059-01 B
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Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Package Outline and Package Dimensions (20 pin SOIC, 300 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches Min Max
Index A rea
E H
A A1 A2 B C D E e H h L
h x 45 o
-2.65 1.10 -2.05 2.55 0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 Basic 10.00 10.65 0.25 0.75 0.40 1.27 0 8
-0.104 0.0040 -0.081 0.100 0.013 0.020 0.007 0.013 0.496 0.512 0.291 0.299 0.050 Basic 0.394 0.419 0.010 0.029 0.016 0.050 0 8
1
2
D
A2
A
A1
e
B
LC
Ordering Information
Part / Order Number
MK2059-01SI MK2059-01SITR
Marking
MK2059-01SI MK2059-01SI
Shipping packaging
Tubes Tape and Reel
Package
20 pin SOIC 20 pin SOIC
Temperature
-40 to +85 C -40 to +85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2059-01 B
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Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com

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